TSMC's CoPoS (Chip-on-Panel-on-Substrate) pilot line began tool deliveries in February 2026 and is on track for full completion by June, with volume production expected between 2028 and 2029. The technology is being developed to address reticle-size constraints on 12-inch wafers, where chips like NVIDIA's Rubin GPU yield as few as 4–7 units per wafer, making panel-format packaging a throughput solution. Warpage at larger substrate sizes is cited as the primary technical barrier to mass production. For financial institutions, this signals that CoWoS will remain the dominant advanced packaging node through at least 2027–28, with CoPoS representing a medium-term supply expansion rather than a near-term constraint relief.
281 other tracked developments touching the same claims.