TSMC CoWoS capacity targets 120–130 KWPM by end-2026, up ~60% from current 75–80 KWPM, as NVIDIA demand surges to ~700K wafers

TSMC's CoWoS advanced packaging capacity stands at 75–80K wafers per month (KWPM) as of late 2025, with a ramp target of 120–130 KWPM by end-2026 via facility optimization rather than new builds, as physical land constraints limit greenfield expansion. NVIDIA alone is projected to consume ~700K CoWoS wafers in 2026 (up ~75% YoY), absorbing the majority of available capacity and squeezing other hyperscalers, Google's 2026 delivery is estimated at 150–180K wafers against a ~240K demand target. To manage the bottleneck, TSMC plans to outsource 240–270K wafers annually to OSATs (primarily Amkor and SPIL), reserving in-house capacity for high-margin silicon interposer and CoWoS-L steps. For financial institutions, this supply granularity confirms CoWoS remains the binding constraint on AI accelerator volume through at least 2026, concentrating execution risk at a single chokepoint that NVIDIA currently controls disproportionately. Also reported by: https://siliconanalysts.com/market-data/cowos-capacity · https://siliconanalysts.com/analysis/foundry-allocation-status-q1-2026