AI chip supply declared binding constraint on compute buildout as TSMC wafer capacity runs at or above 100% utilization

A May 2026 CNAS report documents that AI chip manufacturing, specifically advanced logic wafer fabrication at TSMC and HBM/DRAM production at Samsung, SK Hynix, and Micron, has become the primary bottleneck on AI compute scaling, superseding power as the leading constraint from 2024-2025. TSMC's 3nm node has operated at or above 100% utilization since late 2025, its 2nm capacity is booked through 2028, and memory manufacturers cut fab investment in 2023-2024, meaning new supply is years away; DRAM prices rose over 600% and NAND over 300% in 2025. For financial institutions, this supply inelasticity creates a durable pricing floor for AI chip and memory producers while simultaneously capping the rate at which hyperscalers can deploy announced capex commitments. Also reported by: https://www.datacenterknowledge.com/infrastructure/after-the-power-crunch-ai-infrastructure-hits-a-gpu-wall